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1.
Ide 2013-12-24 02:11:56
NODE ADDRESS
NodeSW1/1SW1/2SW1/3SW1/4SW1/5SW1/6SW1/7SW1/8
0--------
1OffOnOnOnOnOnOnOn
2OnOffOnOnOnOnOnOn
3OffOffOnOnOnOnOnOn
4OnOnOffOnOnOnOnOn
251OffOffOnOffOffOffOffOff
252OnOnOffOffOffOffOffOff
253OffOnOffOffOffOffOffOff
254OnOffOffOffOffOffOffOff
255OffOffOffOffOffOffOffOff
Note:Node address 0 is used for messaging between nodes and must not be used.

A total of 255 node address settings are available. The switches are a binary representation of the decimal node addresses. Switch 1 is the Least Significant Bit and switch 8 is the Most Significant Bit. The switches have the following decimal values: switch 1=1, 2=2, 3=4, 4=8, 5=16, 6=32, 7=64, 8=128. Turn off the switches and add the values of the off switches to obtain the correct node address. (On=0, Off=1)

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2.
Ide 2013-12-24 02:24:32
TIMEOUT CONFIGURATION
Response TimeIdle TimeReconfig. TimeJP1AJP1B
"1190µs1237µs1680msOpenOpen
 563µs624µs1680msClosedOpen
 285µs316µs1680msOpenClosed
 78µs86µs840msClosedClosed
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3.
Ide 2013-12-24 02:30:55
BOOT ROM
SettingJP1C
»Disabled Open
 EnabledClosed
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4.
Ide 2013-12-24 02:35:31
INTERRUPT REQUEST
IRQJP1DJP1EJP1FJP1GJP1H
2OpenOpenOpenOpenClosed
3OpenOpenOpenClosedOpen
4OpenOpenClosedOpenOpen
5OpenClosedOpenOpenOpen
7ClosedOpenOpenOpenOpen
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5.
Ide 2013-12-24 02:36:54


I/O BASE ADDRESS
AddressSW2/1SW2/2SW2/3
260h OnOnOn
290hOnOnOff
2E0hOnOffOn
2F0hOnOffOff
300hOffOnOn
350hOffOnOff
380h OffOffOn
3E0hOffOffOff
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6.
Ide 2013-12-24 02:45:23
BASE MEMORY ADDRESS & BOOT ROM ADDRESS
Base AddressBoot ROM AddressSW2/4SW2/5SW2/6SW2/7SW2/8
»D0000 - D07FFh D2000 - D3FFFhOnOffOffOnOn
 C0000 - C07FFhC2000 - C3FFFhOnOnOnOnOn
 C0800 - C0FFFhC2000 - C3FFFhOnOnOnOnOff
 C1000 - C17FFhC2000 - C3FFFhOnOnOnOffOn
 C1800 - C1FFFhC2000 - C3FFFhOnOnOnOffOff
 C4000 - C47FFhC6000 - C7FFFhOnOnOffOnOn
 C4800 - C4FFFhC6000 - C7FFFhOnOnOffOnOff
 C5000 - C57FFhC6000 - C7FFFhOnOnOffOffOn
 C5800 - C5FFFhC6000 - C7FFFhOnOnOffOffOff
 CC000 - CC7FFhCE000 - CFFFFhOnOffOnOnOn
 CC800 - CCFFFhCE000 - CFFFFhOnOffOnOnOff
 CD000 - CD7FFhCE000 - CFFFFhOnOffOnOffOn
 CD800 - CDFFFhCE000 - CFFFFhOnOffOnOffOff
 D0800 - D0FFFhD2000 - D3FFFhOnOffOffOnOff
 D1000 - D17FFhD2000 - D3FFFhOnOffOffOffOn
 D1800 - D1FFFhD2000 - D3FFFhOnOffOffOffOff
 D4000 - D47FFhD6000 - D7FFFhOffOnOnOnOn
 D4800 - D4FFFhD6000 - D7FFFhOffOnOnOnOff
 D5000 - D57FFhD6000 - D7FFFhOffOnOnOffOn
 D5800 - D5FFFhD6000 - D7FFFhOffOnOnOffOff
 D8000 - D87FFhDA000 - DBFFFhOffOnOffOnOn
 D8800 - D8FFFhDA000 - DBFFFhOffOnOffOnOff
 D9000 - D97FFhDA000 - DBFFFhOffOnOffOffOn
 D9800 - D9FFFhDA000 - DBFFFhOffOnOffOffOff
 DC000 - DC7FFhDE000 - DFFFFhOffOffOnOnOn
 DC800 - DCFFFhDE000 - DFFFFhOffOffOnOnOff
 DD000 - DD7FFhDE000 - DFFFFhOffOffOnOffOn
 DD800 - DDFFFhDE000 - DFFFFhOffOffOnOffOff
 E0000 - E07FFhE2000 - E2FFFhOffOffOffOnOn
 E0800 - E0FFFhE2000 - E2FFFhOffOffOffOnOff
 E1000 - E17FFhE2000 - E2FFFhOffOffOffOffOn
 E1800 - E1FFFhE2000 - E2FFFhOffOffOffOffOff
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7.
Ide 2013-12-24 02:48:20
(0)
8.
Ide 2014-03-30 15:20:34
(0)
9.
Ide 2014-03-30 16:47:47
Example for I/O x2E0 and RAM-Addr. xCD000 (0)

timestamp 2026-03-05 21:41:53